This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-397290, filed Dec. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to the structure of a pad electrode in a semiconductor device.
FIG. 20 is a perspective view showing a pad electrode and its peripheral parts in a semiconductor device according to conventional technologies. FIG. 21 is a plan view showing a pad electrode manufactured based on conventional technologies.
As shown in FIG. 20, a gate electrode 112 of a MOSFET 111 is connected to a first layer wiring 114a through a via wiring 113a and the first layer wiring 114a is connected to a second layer wiring 114b through a via wiring 113b. This second layer wiring 114b is connected to a third layer wiring 114c through a via wiring 113c and the third layer wiring 114c is connected to a pad electrode 100 through a via wiring 113d. 
This pad electrode 100 is a plate electrode having a relatively large area allowing wire bonding and bump connection. The pad electrode 100 is electrically connected to the MOSFET 111 through the via wirings 113a, 113b, 113c and 113d and the wirings 114a, 114b and 114c. 
Also, as shown in FIG. 21A to FIG. 21E, the pad electrode 100 is provided with a slit to make a part thereof form a net or a cut is made in the pattern of the pad electrode 100 as the case may be for the purpose of decreasing stress.
Such a pad electrode 100 has a charging damage problem as the well-known inferior problem. This problem is that a charge is injected into the wirings 114a, 114b and 114c by a plasma used in the manufacturing process and stress is thereby applied to a gate insulating film of the MOSFET 111 with the result that the fundamental characteristics of the MOSFET are deteriorated. A plasma causes a charge to be injected from an exposed surface of a conductor such as the wirings 114a, 114b and 114c. Therefore, the larger the surface area of each of the wirings 114a, 114b and 114c to be connected to the gate electrode 112 is, the more easily a charge from the plasma is collected and the more easily the gate insulating film is damaged.
In view of this, in order to prevent the charging damage, measures are taken to restrict the length of each of the wirings 114a, 114b and 114c connected to the gate electrode 112 thereby decreasing the surface area.
However, as aforementioned, a relatively large area is required for the pad electrode 100 to allow wire bonding and bump connection. Generally, many of pad electrodes 100 have a size of about 50 xcexcm to 100 xcexcm (2500 xcexcm2 to 1xc3x97104 xcexcm2). Although such a pad electrode 100 is a charge collector having a large area, the pad electrode 100 is concerned in many plasma steps including a RIE (Reactive Ion Etching) processing step of the pad electrode 100, a resist ashing step of the pad electrode 100 after it was processed, a step of depositing a passivation film on the pad electrode 100, an etching step for opening a pad window and a step of peeling off a resist after the pad window is opened. Therefore, if the pad electrode 100 has a large area, a charge from a plasma is collected with ease, causing charging damage.
For this, a protective diode is conventionally connected to each pad electrode 100 to avoid the charging damages to the pad electrode 100. However, a recent trend in high speed LSIs is a decrease in the junction capacity to accomplish high speed transistors. This is the same with the case of increasing the withstand voltage of the protective diode. To state examples of recent LSIs, junction withstand voltage has been raised to 10V. As a consequence, a stress of about 10V is applied in a process because the function as a protective diode is insufficient. In light of this, there is the case where only a protective diode section is changed in the ion concentration of ion implantation. In this case, however, the number of steps in the production of the protective diode is increased.
As outlined above, in the structure of the conventional pad electrode, it is difficult to decrease the charging damages without increasing the number of steps in the production of the protective diode.
The present invention has been made to solve the aforementioned problem and it is an object of the present invention to provide a semiconductor device enabling a reduction in charging damages.
The present invention uses the following means to achieve the above object.
A first semiconductor device according to a first aspect of the present invention is a semiconductor device provided with a semiconductor element and a wiring, the device comprising a first split pad electrode which is electrically connected to the semiconductor element through the wiring, a second split pad electrode which is disposed adjacent to and apart from the first split pad electrode and is not electrically connected to the semiconductor element, a passivation film which covers a part of the surface of the second split pad electrode and a non-split pad electrode covering the surfaces of the first and second split pad electrodes which are not covered by the passivation film.
A second semiconductor device according to a second aspect of the present invention is a semiconductor device provided with a semiconductor element and a wiring, the device comprising a first split pad electrode which is electrically connected to the semiconductor element through the wiring and a second split pad electrode which is disposed adjacent to and apart from the first split pad electrode and is not electrically connected to the semiconductor element, wherein pad electrodes each constituted by the first and second split pad electrodes are laminated.
A third semiconductor device according to a third aspect of the present invention is a semiconductor device provided with a signal line and a power line, wherein at least a part of a pad electrode for the signal line uses a split pad electrode which is split into a first split pad electrode which is electrically connected to a semiconductor element through a wiring and a second split pad electrode which is disposed adjacent to and apart from the first split pad electrode and is not electrically connected to the semiconductor element and a pad electrode for the power line uses a non-split pad electrode which is electrically connected to the semiconductor element through a wiring.
A fourth semiconductor device according to a fourth aspect of the present invention is a semiconductor device provided with a semiconductor element and a wiring, the device comprising an island-like first split pad electrode which is electrically connected to the semiconductor element through the wiring, a second split pad electrode which is disposed around and apart from the first split pad electrode and is not electrically connected to the semiconductor element, a passivation film which covers a part of the surface of the second split pad electrode and a connecting member disposed on the exposed surface of a pad electrode constituted by the first and second split pad electrodes, wherein a contact surface between the connecting member and the pad electrode is formed in such a manner as to surround the inner periphery of the second split pad electrode.
A fifth semiconductor device according to a fifth aspect of the present invention is a semiconductor device provided with a semiconductor element and a wiring, the device comprising a first split pad electrode which is electrically connected to the semiconductor element through the wiring, a second split pad electrode which is disposed adjacent to and apart from the first split pad electrode and is not electrically connected to the semiconductor element and a passivation film which covers a part of the surface of the second split pad electrode, wherein the surfaces of the first and second split pad electrodes are exposed in the same opening of the passivation film.
As mentioned above, according to the first to fifth semiconductor devices of the present invention, only the surface area of the first split pad electrode connected to wirings and semiconductor elements can be minimized without changing the effective surface area of the pad electrode. Because the area of a conductor which is to be a charge introduction port in a plasma step in the production of a semiconductor device is therefore decreased, charging damages can be prevented and the deterioration of the semiconductor device can be prevented. In addition, a contact surface required for bonding and the like can be secured, enabling sufficient bonding.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.